In shared memory, multi-processor computer systems, cache miss latency has a significant effect on system performance. (In the context of the invention, “processor” includes, but is not limited to, central processing units (CPUs) and I/O processing agents.) As those skilled in the art will understand, a “cache miss” occurs when a processor checks its cache for data and discovers that the desired data is not in the cache. A “cache miss” is the opposite of a “cache hit,” which occurs when the requested information is in the cache. If a cache miss occurs, the processor must request the desired data, referred to as a “cache line,” from the computer system's memory subsystem. The time it takes a processor to check its cache, discover that the data is not in the cache, request the desired data from the memory subsystem, and receive the data from the memory subsystem, is time during which the processor is idle, and is referred to as cache miss latency.
In a large system, cache miss latency can be extremely large, particularly where a processor requests ownership of a cache line owned by a different processor located at a remote cell. A cell is a sub-module of the system and typically has a number of system resources, such as central processing units (CPUs), central agent controllers, input/output (I/O) processing units, and memory. Cells can be configured as a single shared memory domain or as part of multiple cells grouped together to form a shared memory domain. Several steps are involved in transferring ownership of a cache line between processors, and each step increases cache miss latency.